In traditional continuous array memory architecture 100, illustrated in FIG. 1, the memory cells 110 along a row 112 of cells are “turned on” when the row decoder 114 selects the word-line 116 connected to the row 112 of memory cells. When the word-line 116 is activated, each of the cells 110 along that particular row are activated and the data content of each memory cell 110 is transferred to a respective bit-line 118. The bit-lines 118 are shared among the memory cells 110 of different rows 112 and are situated in a cell column 120, but, at a given time, only one cell 110 in each column 120 can transfer its data through its corresponding bit line 118. The column decoder 122 then selects which ones of the cells 110 of the row 112 will transfer their data to the outputs 124 of the memory chip by choosing the appropriate bit-lines 118.
This type of memory architecture, referred to as continuous array architecture, is still in use. Continuous array architecture and its associated read/write scheme are considered inefficient because in practice only a small number of cells need to be “ON” at any given time, and turning ON all the memory cells of a given row draws unnecessary current and needlessly increases power consumption.
Today's most memory designs utilize an architecture frequently referred to as block architecture, in which only a subset or a block of the memory cells are turned ON at a time. This architecture offers substantial power savings and increased speed.
In typical block architecture the memory array is split into separate blocks. Each block includes multiple memory cells, bit-lines connected to each column of memory cells which are selected by a column decoder, global word-lines which are selected by a row decoder, and groups of local word-lines. During operation, a block of memory cells is activated by a block signal. A block signal combines with a selected global word-line within the selected block to activate a local word-line and the corresponding memory cells. A local word-line will be activated only when both the appropriate block signal and the corresponding global word-line are activated. When a global word-line is selected, a local word-line is activated such that only a fraction of the memory cells in a given row are “turned on,” rather than the entire row of memory cells. Therefore, less current is drawn and power consumption decreases.
However, to date, the main focus of the prior art in the area of low power memory design has only been to improve decoding circuits and the access paths (read/write paths).